Post place and route design-technology co-optimization for scaling at single-digit nodes with constant ground rules

Mattii, L; Milojevic, D; Debacker, P; Berekovic, M; Sherazi, SMY; Chava, B; Bardon, MG; Schuddinck, P; Rodopoulos, D; Baert, R; Gerousis, V; Ryckaert, J; Raghavan, P

Mattii, L (reprint author), Braunschweig Univ Technol, Dept Integrated Circuit Design EIS, Braunschweig, Germany.; Mattii, L (reprint author), Cadence Design Syst Inc, San Jose, CA 95134 USA.

JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS, 2018; 17 (1):

Abstract

Standard-cell design, technology choices, and place and route (P&R) efficiency are deeply interrelated in CMOS technology nodes below 10 nm, where......

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