A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC

Ohhata, K; Hayakawa, D; Sewaki, K; Imayanagida, K; Ueno, K; Sonoda, Y; Muroya, K

Ohhata, K (reprint author), Kagoshima Univ, Dept Elect & Elect Engn, Kagoshima 1-21-40, Kagoshima, Japan.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018; 26 (9): 1777

Abstract

In this paper, we propose a time-based analog-to-digital converter (ADC) architecture combining a flash ADC and vernier time-to-digital converter (TDC......

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