Performance Optimization in Flip Flop Circuit Design

NathSaha, H; Joshi, P; Chattopadhyay, A; Deb, B; Ghosh, A; Kumari, P; Mahato, DK; SayantaniChoudhuri; Bhattacharjee, S; Chattopadhyay, S; Dash, P; BijoyGharai, B

NathSaha, H (reprint author), Inst Engn & Management, Dept Elect & Elect Engn, Kolkata, India.

2018 IEEE 8TH ANNUAL COMPUTING AND COMMUNICATION WORKSHOP AND CONFERENCE (CCWC), 2018; (): 421

Abstract

In delay flip flop the storing of data get restricted due to leakage current which can limit flip flop from performing its operation. The 5T proposed ......

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