Is ESD Protection Design Planning for Large SoC Verified During SoC Floorplan Design Stage?-MedSci.cn

Is ESD Protection Design Planning for Large SoC Verified During SoC Floorplan Design Stage?

Trivedi, NJ; Carn, B; Poal, A

Trivedi, NJ (通讯作者)，Intel Technol, Bangalore 560037, Karnataka, India.

2022 44TH ANNUAL EOS/ESD SYMPOSIUM (EOS/ESD), 2022; ():

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